View ISL12082IB8Z-T_8984889.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn6731 rev 4.00 page 1 of 28 sep 25, 2015 fn6731 rev 4.00 sep 25, 2015 isl12082 i2c-bus real time clock with two interrupts, alarm, and timer, low power rtc with battery reseal, 2 irqs, hundredths of a second time and crystal compensation datasheet the isl12082 device is a low power real time clock with timing and crystal compensation , clock/calendar, power fail indicator, 2 irqs, periodic or p olled alarm, tim er/watchdog, and intelligent battery backup switching. the oscillator uses an external , low-cost 32.768khz crystal. the real time clock tracks time w ith separate registers for hours, minutes, seconds and h undredths of a second. the device has calendar registers f or date, month, year and day of the week. the calendar is accurate through 2099, with automatic leap year correction. pinouts isl12082 (8 ld soic) top view isl12082 (10 ld msop) top view features ? real time clock/calendar - tracks time in hours, m inutes, se conds, and hundredths of a second - day of the week, day, month, and year ? 4 selectable frequency outputs ? alarm - settable to the second, minute, hour, day of the week, day, or month - single event or pulse interrupt mode ?timer - 4 selectable timer functions - 4 selectable timer clock frequencies - single event or pulse interrupt mode ? automatic backup to battery or supercapacitor ? power failure detection ? battery reseal ? ? on-chip oscillator compensation ?i 2 c interface - 400khz data transfer rate ? 800na battery supply current ? small package options - 8 ld soic package - 10 ld msop package ? pb-free (rohs compliant) applications ? utility meters ? hvac equipment ? audio/video components ? set-top box/television ? modems ? network routers, hubs, switches, bridges ? cellular infrastructure equipment ? fixed broadband wireless equipment ? pagers/pda ? pos equipment ? test meters/fixtures ? office automation (copiers, fax) ? home appliances ? computer products 1 2 3 4 8 7 x1 x2 gnd v dd irq1 /f out scl sda irq2 5 6 vdd irq1 /f out scl sda irq2 x1 x2 v bat nc 1 2 3 4 5 10 9 8 7 6 gnd n o l o n g e r a v a i l a b l e o r s u p p o r t e d
isl12082 fn6731 rev 4.00 page 2 of 28 sep 25, 2015 . block diagram ordering information part number (note) part marking v dd range (v) temp. range (c) package (rohs compliant) pkg. dwg. # isl12082ib8z 12082 ibz 2.7 to 5.5 -40 to +85 8 ld soic m8.15 ISL12082IB8Z-T* 12082 ibz 2.7 to 5.5 -40 to +85 8 ld soic (tape and reel) m8.15 isl12082iuz (no longer available or supported) 12082 2.7 to 5.5 -40 to +85 10 ld msop m10.118 isl12082iuz-t* (no longer available or supported) 12082 2.7 to 5.5 -40 to +85 10 ld msop (tape and reel) m10.118 *please refer to tb347 for det ails on reel s pecifications. note: these intersil pb-free plas tic packaged products employ sp ecial pb-free material sets, m olding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020. i 2 c interface rtc control logic alarm frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl x1 x2 v dd v bat irq1 /f out internal supply v trip seconds minutes hours day of week date month year control registers timer irq2
isl12082 fn6731 rev 4.00 page 3 of 28 sep 25, 2015 pin descriptions pin number symbol description soic msop 1 1 x1 the x1 pin is the input of an inverting amplifier and is in tended to be connected to one pin of an external 32.768khz quartz crystal. x1 can also be driven directly from a 32.768khz source. 2 2 x2 the x2 pin is the output of an inverting amplifier and is i ntended to be connected to one pin of an external 32.768khz quartz crystal. -3v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin should be tied to ground if not used. 3 4 gnd ground - 5 nc no connect 46irq2 interrupt output 2 is a multi-functional pin that can be used as alarm interrupt or tim er interrupt pin. the function is set via the c onfiguration register. 5 7 sda serial data (sda) is a bi-directional pin used to transfer serial data into and out of the device. it has an open drain output and may be wire ored with other open drain or ope n collector outputs. 6 8 scl the serial clock (scl) inpu t is used to clock all serial d ata into and out of the device. 79irq1 /f out interrupt output 1/frequency output is a multi-functional pin that can be used as alarm interrupt or fre quency output pin. the function is set via the configuration register. 810v dd power supply
isl12082 fn6731 rev 4.00 page 4 of 28 sep 25, 2015 absolute maximum ratings thermal information voltage on v dd , v bat , scl, sda, irq1 /f out and irq2 pins (respect to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6.5v voltage on x1 and x2 pins (respect to gnd) . . . . . . . . . . . . .-0.5v to v dd + 0.5 (v dd mode) -0.5v to v bat + 0.5 (v bat mode) thermal resistance (typical, note 1) ? ja (c/w) 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10 ld msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 maximum storage temperature range . . . . . . . . . .-65c to +1 50c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. dc operating characteristics - rtc temperature = -40c to +85c, unless otherwise stated. symbol parameter conditions min (note 6) typ (note 5) max (note 6) units notes v dd main power supply 2.7 5.5 v v bat battery supply voltage 1.8 5.5 v i dd1 supply current v dd = 5v 2.8 6 a 2, 3 v dd = 3v 1.6 4 a i dd2 supply current with i 2 c active v dd = 5v 40 120 a 2, 3 i dd3 supply current (low power mode) v dd = 5v, lpmode = 1 2.3 5 a 2 i bat battery supply current v bat = 3v, +25c 800 950 na 2, 9 i li input leakage current on scl -1 0.1 +1 a i lo i/o leakage current on sda -1 0.1 +1 a v trip v bat mode threshold 1.8 2.15 2.4 v 9 v triphys v trip hysteresis 36 mv 7, 9 v bathys v bat hysteresis 53 mv 7, 9 irq1 /f out and irq2 v ol output low voltage v dd = 5v i ol = 3ma 0.02 0.4 v v dd = 2.7v i ol = 1ma 0.02 0.4 v power-down timing timing temperature = -40c to +85c, unless otherwise stated. symbol parameter conditions min (note 6) typ (note 5) max (note 6) units notes v dd sr- v dd negative slewrate 5 v/ms 4, 9 serial interface specifications over the recommended operating c onditions, unless otherwise spe cified. symbol parameter test conditions min (note 6) typ (note 5) max (note 6) units notes v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v 7, 8 v ol sda output buffer low voltage, sinking 3ma 0 0.02 0.4 v
isl12082 fn6731 rev 4.00 page 5 of 28 sep 25, 2015 cpin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf 7, 8 f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition 1300 ns t low clock low time measured at the 30% of v dd crossing 1300 ns t high clock high time measured at the 70% of v dd crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window 0 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edg e both crossing 70% of v dd 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window 0ns t r sda and scl rise time from 30% to 70% of v dd 20 + 0.1 x cb 300 ns 7, 8 t f sda and scl fall time from 70% to 30% of v dd 20 + 0.1 x cb 300 ns 7, 8 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 7, 8 rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ? to ~2.5k ? for cb = 40pf, max is about 15k ?? to ~20k ? 1k ? 7, 8 notes: 2. irq and f out inactive. 3. lpmode = 0 (default). 4. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 5. typical values are for t = +25c and 3.3v supply voltage. 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. t emperature limits established b y characterization and are not production tested. 7. limits should be considered ty pical and are not production te sted. 8. these are i 2 c specific parameters and are not tested, however, they are use d to set conditions for testing devices to validate specification. 9. parameters are for 10 ld msop package only. serial interface specifications over the recommended operating c onditions, unless otherwise spe cified. (continued) symbol parameter test conditions min (note 6) typ (note 5) max (note 6) units notes
isl12082 fn6731 rev 4.00 page 6 of 28 sep 25, 2015 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don???e?et changes allowed changing: state not known n/a center line is high impedance
isl12082 fn6731 rev 4.00 page 7 of 28 sep 25, 2015 typical performance curves temperature is +25c unless otherwise specified figure 1. i bat vs v bat figure 2. i bat vs temperature at v bat = 3v figure 3. i dd1 vs temperature figure 4. i dd1 vs v cc with lpmode on and off figure 5. i dd1 vs f out at v dd = 3.3v figure 6. i dd1 vs f out at v dd = 5v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat (v) i bat (a) 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -40 -20 0 20 40 60 80 temperature (c) i bat (a) 1.0 1.5 2.0 2.5 3.0 3.5 -40-200 20406080 v dd (v) i dd (a) v dd = 3.3v v dd = 5v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) i cc (a) lp mode on lp mode off 1.5 2.5 3.5 1 512 4096 32768 f out (hz) i dd (a) 2.5 3.5 4.5 1 512 4096 32768 f out (hz) i dd (a)
isl12082 fn6731 rev 4.00 page 8 of 28 sep 25, 2015 general description the isl12082 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, timer/w atchdog, and intelligent batte ry backup switching. the oscillator uses an external , low-cost 32.768khz crystal. the real time clock tracks time w ith separate registers for hours, minutes, seconds, and su b-seconds. the device has calendar registers for date, mont h, year and day of the week. the calendar is accurate thro ugh 2099, with automatic leap year correction. the isl12082's powerful alarm can be set to any clock/calendar value for a match . for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register, or the device can be configured to provide a hardware interrupt via the irq1 /f out or irq2 pin. there is a repeat mode for the alarm allowing a periodic interrupt every minute , every hour, every day, etc. the isl12082 has a powerful time r function. the timer status is available by checking the status r egister, or the device can be configured to provide a hardware interrupt via the irq2 pin. the device also offers a backup power input pin. this v bat pin allows the device to be backed up by battery or supercapacitor with automatic s witchover from v dd to v bat . the entire isl12082 device is fully operational from 2.7v to 5.5v and the clock/calendar portion of the device remains fully operational down to 1.8v (standby mode). pin description x1, x2 the x1 and x2 pins are the input and output, respectively, of a n inverting amplifier. an external 32.768khz quartz crystal is us ed with the isl12082 to supply a timebase for the real time clock. internal compensation circuitry pr ovides high accuracy over the operating temperature range from -40c to +85c. this oscillator compensation network can be used to calibrate the crystal timing accuracy over-temperature either during manufacturing or with an exte rnal temperature sensor and microcontroller for active compensation. the device can also be driven directly from a 32. 768khz source at pin x1. v bat this input provides a backup su pply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin can b e connected to a battery, a supercapacitor or tied to ground if not used. irq1 /f out (interrupt output 1/frequency output) the irq1 /f out is an open drain output. this dual function pin can be used as an interrupt or frequency output pin. the irq1 /f out mode is selected via the irq1e bit of the control register (address 08h). ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. ? frequency output mode. the pin outputs a clock signal which is related to the crystal frequency. the frequency output is user selecta ble and enabled via the i 2 c bus. irq2 (interrupt output 2) the irq2 is an open drain output. the irq2 pin can be used as an alarm interrupt or timer interrupt output pin. the irq2 mode is selected via the irq2e control bits of the control re gister (address 08h). the pin provides an interrupt signal outpu t. this signal notifies a hos t processor that an alarm or ti mer has occurred and requests action. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gate d). it is disabled when the backup power supply on the v bat pin is activated to minimiz e power consumption. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it has an open dra in output and may be ored with other open drain or open collecto r outputs. the input buffer is always active (not ga ted) in normal mode. an open drain output requires the use of a pull-up resistor. th e output circuitry controls the fa ll time of the output signal wi th the use of a slope controlled pull-down. the circuit is designe d for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the v bat pin is activated. figure 7. standard output load for testing the device with v dd = 5.0v 1533 ? 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circui t for v dd = 5v sda irq1 /f out and irq2 figure 8. recommended crystal connection x1 x2
isl12082 fn6731 rev 4.00 page 9 of 28 sep 25, 2015 v dd , gnd chip power supply and ground pi ns. the device will operate with a power supply from 2.7v to 5.5vdc. a 0.1f decoupling capacitor is recommended on the v dd pin to ground. functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the isl12082 for up to 10 years . another option is to use a supercapacitor for applications where v dd is interrupted for up to a month. see the a pplication section o n page 23 for more information. normal mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys ? 50mv condition 2: v dd < v trip where v trip ? 2.2v battery backup mode (v bat ) to normal mode (v dd ) the isl12082 device wil l switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys ?? 50mv condition 2: v dd > v trip + v triphys where v triphys ? 30mv these power control situations a re illustrated in figures 9 and 10. the i 2 c bus is deactivated in battery backup mode to provide lower power. aside from this, a ll rtc functions are operational during battery backup mode. exc ept for scl and sda, all the inputs and outputs of the isl12082 are acti ve during battery backup mode unless disabled via the control register. power failure detection the isl12082 provides a real time clock failure bit (rtcf, address 0bh) to detect total pow er failure. it allows users to determine if the device has pow ered up after having lost all power to the device (both v dd and v bat ). low power mode the normal power switching of the isl12082 is designed to switch into battery ba ckup mode onl y if the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. another mode, called low power mode, is available to all ow direct switching from v dd to v bat without requiring v dd to drop below v trip . since the additional monitoring of v dd vs v trip is no longer needed, that circuitry is s hut down and less power is used while operating from v dd . power savings are typically 600na at v dd = 5v. low power mode is activated via the lpmode bit in the control and status registers. low power mode is usefu l in systems where v dd is normally higher than v bat at all times. the dev ice will switch from v dd to v bat when v dd drops below v bat , with about 50mv of hysteresis to preven t any switchback of v dd after switchover. in a system with a v dd = 5v and backup lithium battery of v bat = 3v, low power mode can b e used. however, it is not recommended to use low power mode in a system with v dd = 3.3v 10%, v bat ? 3.0v, and when there is a finite i-r voltage drop in the v dd line. interseal? and reseal? battery saver the isl12082 has the interse al? battery saver, which prevents initial battery current drain before it is first used. for example, battery-backed rtcs are commonly packaged on a board with a battery c onnected. in order to preserve battery life, the isl12082 will not draw any power from the battery source until after the device is first powered up from the v dd source. thereafter, the device w ill switchover to battery backu p mode whenever v dd power is lost. v bat - v bathys v bat v bat + v bathys battery backup mode v dd v trip 2.2v 1.8v figure 9. battery switchover when v bat < v trip figure 10. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v
isl12082 fn6731 rev 4.00 page 10 of 28 sep 25, 2015 the isl12082 has the reseal? function, which allows the device to enter into the inters eal? battery saver mode after manufacture testing for board functionality. to use the reseal? function, simply set reseal bit to 1 (address 07h) after the testing is completed. it will enable the interseal? battery saver mode a nd prevents battery current drain before it is first used. real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of sub-second, second, minute, hour , day of week, date, month, and year. the rtc also has leap-year correction. the rtc also corrects for months havin g fewer than 31 days and has a bit that controls 24 hour or am/pm format. when the isl12082 powers up after the loss of both v dd and v bat , the clock will not begin incrementing until at l east one byte is written to th e clock register. accuracy of the real time clock the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time base f or the rtc. since the resonan t frequency of a crystal is temperature dependen t, the rtc performance will also be dependent upon temperature. the frequency deviation of the crystal is a function of the tur nover-temperature of the crysta l from the crystals nominal fre quency. for example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. these param eters are available from the crystal manufacturer. the isl12082 pr ovides on-chip crystal compensation networks to adj ust load capacitance to tune oscillator frequency from - 94ppm to +140ppm. for more detailed information, see app lication section on page 23. single event and interrupt the alarm mode is enabled via the alm e bit (address 08h). choosing single event or inte rrupt alarm mode i s selected via the im bit (address 08h). note that when the frequency output function is enabled, the al arm function is disabled. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occ urs in single event mode, an irq1 /f out and/or irq2 pin will be pulled low and the alarm status bit (alm) will be set to 1. the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year ( if at least the nth month is set). during pulsed interrupt mode, t he irq1 /f out and/or irq2 pin will be pulled low for 210ms and the alarm status bit (alm) will be set to 1. note: the alm bit can be rese t by the user or cleared automatically using the auto reset m ode (see arst bit, address 07h). the alarm function can be enab led/disabled during battery backup mode using the fobatb b it (address 08h). for more information on the alarm, see alarm registers on page 14. frequency output mode the isl12082 has the option to provide a frequency output signal using the irq /f out pin. the frequency output mode is set by using the fo bits to sel ect 4 possible output frequency values from 1khz to 32.768k hz. the frequency output can be enabled/disabled during batt ery backup mode using the fobatb bit (address 08h). i 2 c serial interface the isl12082 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compat ible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). oscillator compensation the isl12082 provides the option of timin g correction due to temperature variation of the c rystal oscillator for either manufacturing calibration or a ctive calibration. the total possible compensation is typically -94ppm to +140ppm. two compensation mechanisms that ar e available are as follows: 1. an analog trimming (atr) r egister that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. the individual digital capacitor is selectable from a range of 9pf to 40.5pf (based upon 32.758khz). this translates to a calculated compensation of approximately -34ppm to +80ppm. see atr description on page 23. 2. a digital trimming register (dtr) that can be used to adjust the timing counter by -63p pm to +126ppm. see dtr description on page 23. also provided is the ability to adjust the crystal capacitance when the isl12082 switches from v dd to battery backup mode. register descriptions the battery-backed registers are accessible following a slave byte of 1101111x and reads or writes to addresses [00h:1fh]. the defined addresse s and default values are described in table 1. address 16h to 1eh are not used. reads or writes to addresses 16h to 1eh will not affect operation of the device bu t should be avoided. register access the contents of the r egisters can be modif ied by performing a byte or a page write operation d irectly to any register address . the registers are divided into 4 sections. these are: 1. real time clock (8 bytes): a ddress 00h to 06h , and 1fh, with address 1fh as read-only byte. 2. control and status (5 by tes): address 07h to 0bh. 3. alarm (6 bytes): a ddress 0ch to 11h.
isl12082 fn6731 rev 4.00 page 11 of 28 sep 25, 2015 4. timer (4 bytes): address 12h to 14h, with address 14h as write-only byte and read back 0.. there are no addr esses above 1fh. address 15h to 1eh are not used. reads or writes to addresses 15h to 1eh will not affect operation of the device bu t should be avoided. write capability is allowable into the rtc registers (00h to 06 h, and 1fh) only when the wrtc bit (bit 4 of address 07h) is set to 1. a multi-byte read or write operation is limited to one section per operation. access to another section requires a new operation. a read or write can begin at any address within the section. a register can be r ead by performing a random read at any address at any time. this retur ns the contents of that register location. additional registers are read by performing a sequential read. for the rtc a nd alarm registers, the read instruction latches all clock registers into a buffer, so an up date of the clock does not change the time being read. a sequential read will not result in the outpu t of data from the memory arra y. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the address remains at the previous address +1 so the user can execute a current address read and conti nue reading the next register. table 1. register memory map addr. section reg name bit reg 7 6 5 4 3 2 1 0 range default 1fh rtc ss ss23 ss22 ss21 ss20 ss13 ss12 ss11 ss10 0 to 99 00h 00h sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn of mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 80h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 00h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 00h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 06h dw00000dw12dw11dw100 to 600h 07h status sr arst xstop reseal wrtc tmr alm bat rtcf n/a 03h 08h control int im alme lpmode fobatb irq2e irq1e fo1 fo0 n/a 00h 09h tmrc tim tmre tmod1 tmod0 0 0 tclk1 tclk0 n/a 00h 0ah atr bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 n/a 00h 0bh dtr 0 0 dtr5 dtr4 dtr3 dtr2 dtr1 dtr0 n/a 80h 0ch alarm0 sca esca asc22 asc21 asc20 asc13 asc12 asc11 asc10 00 to 59 00h 0dh mna emna amn22 amn21 amn20 amn13 amn12 amn11 amn10 00 to 59 00h 0eh hra ehra 0 ahr21 ahr20 ahr13 ahr12 ahr11 ahr10 0 to 23 00h 0fh dta edta 0 adt21 adt20 adt13 adt12 adt11 adt10 1 to 31 00h 10h moa emoa 0 0 amo20 amo13 amo12 amo11 amo10 1 to 12 00h 11h dwaedwa0000adw12adw11adw100 to 600h 12h timer tdat tdat7 tdat6 tdat5 tdat4 tdat3 tdat2 tdat1 tdat0 0 to 255 00h 13h tcnt tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 0 to 255 00h 14h tsdat x tsdat6 tsdat5 tsdat4 tsdat3 tsdat2 tsdat1 tsdat0 0 to 99 00h
isl12082 fn6731 rev 4.00 page 12 of 28 sep 25, 2015 real time clock registers addresses [00h to 06h, and 1fh] rtc registers (sc, mn, hr, dw, dt, mo, yr, ss) these registers depic t bcd representations of the time. as such, sc (seconds, address 00h ) and mn (minutes, address 01h) range from 0 to 59, hr (hour, address 02h) can either be a 12-hour or 24-hour mode, dt (dat e, address 03h) is 1 to 31, mo (month, address 04h) is 1 to 12, yr (year, address 05h) is 0 to 99, dw (day of the week, address 03h) is 0 to 6, and ss (sub-seconds/hundredths of a se cond, address 1fh) is 0 to 99. the ss register is read only. a page read operation to read all the rtc regsiters is possible by setting up the address to 1fh then do a page r ead of 8 bytes. the f irst data read will be ss, then follows by sc, mn, hr, dt, mo, yr, and dw at the end. this is done by using addre ss wrap around feature of the isl12082. the address wraps around from 1fh to 00h in page read instruction. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the c ycle 0-1-2-3-4-5-6-0-1-2- the assignment of a numerical v alue to a specific day of the week is arbitrary and may be deci ded by the syst em software designer. the default va lue is defined as 0. bit d7 of mn register contains t he oscillator fail indicator bi t (of). this bit is set to a 1 when there is no oscillation on x1 pin. the of bit can only be reset by having an oscillation on x 1 and a write operation to reset it. 24 hour time if the mil bit o f the hr register is 1, the rtc uses a 24-hou r format. if the mil bit is 0, the rtc uses a 12-hour format an d hr21 bit functions as an am /pm indicator with a 1 representing pm. the clock defaults to 12-hour formattime with hr21 = 0. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. y ears divisible by 100 are not l eap years, unless they are also divi sible by 400. this means that t he year 2000 is a leap year, the year 2100 is not. the isl12082 do es not correct for the leap year in the year 2100. control and status registers addresses [07h to 0bh] the control and status regist ers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) [address 07h] the status register is located in the memory map at address 0bh. this is a volatile register that provides either control o r status of rtc failure, battery mode, alarm trigger, write protection of clock counter, c rystal oscillator enable and auto reset of status bits. real time clock fail bit (rtcf) this bit is set to a 1 after a total power failure. this is a read only bit that is set by hardware (isl12082 internally) when the device powers up after having lost all power (both v dd and v bat go to 0v). the bit is s et regardless of whether v dd or v bat is applied first. the loss of o nly one of the supplies does not set the rtcf bit to 1. o n power-up after a total power failure, all registers are set to their default states and the clock will not increment until at leas t one byte is written to the cl ock register. the first valid writ e to the rtc se ction after a complete power failure resets the rtcf bit to 0 (writing one byte is sufficient). battery bit (bat) this bit is set to a 1 when the device enters battery backup mode. this bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to thi s bit in the sr can onl y set it to 0, not 1. alarm bit (alm) this bit announces that the ala rm matches the real time clock. if there is a match, the respecti ve bit is set to 1. this bit can be manually reset to 0 by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to 0, not 1. note: an alarm bit th at is set by an alarm occurring during an sr read operation will remain se t after the read operation is complete. timer bit (tmr) this bit announces that the time r has expired. if the timer has expired, the respective bit is set to 1. this bit can be manu ally reset to 0 by the user or aut omatically reset by enabling the auto-reset bit (see arst bit). a w rite to this bit in the sr ca n only set it to 0, not 1. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc timing registers. the factory de fault setting of this bit is 0 . upon initialization or power-up, the wrtc must be set to 1 to enable the rtc. upon the completi on of a valid write (stop), the rtc starts counting. the rtc internal 1hz signal is synchronized to the s top condition during a valid write cycle. reseal? (reseal) the reseal? enables the device enter into the interseal? battery saver mode after board f unctional testing. the factory default setting of this bit is 0 to enable the backup battery table 2. status register (sr) addr 7 6 5 4 3 2 1 0 07h arst xstop reseal wrtc tmr alm bat rtcf default 0 0 1 0 0 0 1 1
isl12082 fn6731 rev 4.00 page 13 of 28 sep 25, 2015 operation. to use the reseal? function, simply set reseal bit to 1 after the testing is completed. it will enable the inter seal? battery saver mode and prevents battery current drain before it is first used. upon the next v dd powerup, the bit will reset to 0 and the backup battery will be utilized. crystal oscillator enable bit (xstop) this bit enables/disables the c rystal oscillator. when the xstop is set to 1, the oscillator is disabled. the xstop bit is set to 0 on power-up for normal operation. auto reset enable bit (arst) this bit enables/disables the aut omatic reset of the bat, alm and tmr status bits only. when ar st bit is set to 1, these status bits are reset to 0 aft er a valid read of the respecti ve status register (with a valid st op condition). when the arst is cleared to 0, the user mu st manually reset the bat, alm and tmr bits. interrupt control register (int) [address 08h] frequency out control bits (fo <1:0>) these bits select the ou tput frequency at the irq /f out pin. irq1e must be set to 0 for frequency output at the irq /f out pin. see table 4 for frequency selection. note: the falling edge of 1hz frequency output is synchronized with the seconds. irq function selection bits (irq1e, irq2e) these bits select the function of irq1 /f out and irq2 pin. see table 5 for function selection of irq1 /f out pin and table 6 for function selection of irq2 pin. frequency output and interrupt bit (fobatb) this bit enables/disables the irq1 /f out pin during battery backup mode (i.e. v bat power source active). when the fobatb is set to 1, the irq1 /f out pin is disabled during battery backup mode . this means that both the frequency output and alarm output funct ions are disabled. when the fobatb is cleared to 0, the irq1 /f out pin is enabled during battery backup mode. low power mode bit (lpmode) this bit enables/disables low power mode. with lpmode = 0, the device wil l be in normal mode and the v bat supply will be used when v dd < v bat - v bathys and v dd < v trip . with lpmode = 1, t he device will be in low power mode and the v bat supply will be used when v dd isl12082 fn6731 rev 4.00 page 14 of 28 sep 25, 2015 to 11h). when the im bit is cleared to 0, the alarm will oper ate in standard mode, where the irq1 /f out and/or irq2 pin will be tied low until the alm status b it is cleared to 0. the im bit is set to 0 on power-up. analog trimming register (atr) [address 0ah] analog trimming register (atr<5:0>) six analog trimming bits, atr0 to atr5 , are provided in order to adjust the on-chip load capa citance value for frequency compensation of the r tc. each bit has a different weight for capacitance adjustment. for e xample, using a citizen cfs- 206 crystal with different atr bit combinations provides an estimated ppm adjustment ran ge from -34ppm to +80ppm to the nominal frequency compens ation. the combination of analog and digital trimming can give up to -97ppm to +206ppm of total adjustment. the effective on-chip se ries load capacitance, c load , ranges from 4.5pf to 20.25pf with a mid-scale value of 12.5pf (default). c load is changed via two digitally controlled capacitors, c x1 and c x2 , connected from t he x1 and x2 pins to ground (see figure 11). the value of c x1 and c x2 are given in equation 1: the effective series load capacitance is the combination of c x1 and c x2 in equation 2: for example, c load (atr = 00000) = 12.5pf, c load (atr = 100000) = 4.5pf and c load (atr = 011111) = 20.25pf. the entire range for th e series combination of load capacitance goes from 4.5pf to 20.25pf in 0.25pf steps. note that these are typical values. battery mode atr selection (bmatr <1:0>) since the accuracy of the crystal oscillator is dependent on th e v dd /v bat operation, the isl12082 provides the capability to adjust the capaci tance between v dd and v bat when the device switches between power sources. digital trimming register (dtr) [address 07h] digital trimming r egister (dtr<5:0>) six digital trimming bits, dtr0 to dtr5 , are provided to adjust the average number of counts per second and average the ppm error to achieve better accuracy. ? dtr5 is a sign bit. dtr5 = 0 means frequency compensation is < 0. dtr 5 = 1 mean s frequency compensation is > 0. ? dtr<4:0> are scale bits. wit h dtr5 = 0, dtr<4:0> gives 2.0345ppm adjustme nt per step. with dtr5 = 1, dtr<4:0> gives 4.0690pp m adjustment per step. a range from -63.0696ppm to +126.139ppm can be represented by using these 6 bits. for example, with dtr = 11111, the digital adjustment is (1111b[15d]*4.0690) = +126.139ppm. with dtr = 01111, the digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm. alarm registers addresses [address 0ch to 11h] the alarm register bytes are set up identical to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = 1). the se enable bits specify which alarm registers (seconds, minu tes, etc) are used to make the comparison. note that there is no alarm byte for year and sub- second, and the register order for alarm register is not a 100% matching to the rtc register so please take caution on programming the alarm function. im bit alarm pulse/even t interrupt function 0 single time event set by alarm 1 repetitive/recurring time event set by alarm table 7. analog trimming register (atr) addr7 6 543210 0ah bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 default0 0 000000 figure 11. diagram of atr c x1 x1 x2 crystal oscillator c x2 c x 16 b5 ? 8b4 4b3 2b2 1b1 0.5b0 9 + ? + ? + ? + ? + ? + ?? pf = (eq. 1) c load 1 1 c x1 ---------- - 1 c x2 ---------- - + ?? ?? ---------------------------------- - = c load 16 b5 ? 8 b4 4 b3 2 b2 1 b1 0.5 b0 9 + ? + ? + ? + ? + ? + 2 --------------------------------------------------------------- -------------------------------------------------------------- ?? ?? pf = (eq. 2) bmatr1 bmatr0 delta capacitance (c bat to c vdd ) 0 0 0pf 0 1 -0.5pf ( ? +2ppm) 1 0 +0.5pf ( ? -2ppm) 1 1 +1pf ( ? -4ppm) table 8. digital trimming register (dtr) addr 7 6 543210 07h 0 0 dtr5 dtr4 dtr3 dtr2 dtr1 dtr0 default0 0 000000
isl12082 fn6731 rev 4.00 page 15 of 28 sep 25, 2015 the alarm function wo rks as a comparison between the alarm registers and the rt c registers. as t he rtc advances, the alarm will be triggered once a match occurs between the alarm registers and the rt c registers. any o ne alarm register, multiple registers, or all regis ters can be enabled for a match . there are two ala rm operation modes: single event and periodic interrupt mode: ? single event mode is enabled by setting the alme bit to 1, the im bit to 0, and irq1e bit to 1 and/or irq2e bit t o 0. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm status bit is set to 1 and the irq1 /f out and/or irq2 output will be pulled low and will remain low until the alm status bit is reset to 0. th is can be done manually or by using the auto-reset feature. ? periodic interrupt mode is enabled by setting the alme bit to 1, the im bit to 1, and i rq1e bit to 1 and/or irq2e bi t to 0. the irq1 /f out and/or irq2 output will now be pulsed each time an alarm occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications s uch as security cameras or utility meter reading. to clear an alarm, the alm status bit must be set to 0 with a write. note that if the arst b it is set to 1 (address 07h, bi t 7), the alm bit will aut omatically be clear ed when the status register is read. following are examples of both single event and periodic interrupt mode alarms. example 1 C alarm set with si ngle interrupt (im = 0) a single alarm will occur on january 1 at 11:30am. a. set alarm regi sters as follows: b. set the alme bit as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30am on january 1 (after seconds changes from 59 to 00) b y setting the alm bit in the status register to 1 and also bringing the irq1 /f out and irq2 output low if irq1e bit is set to 1 and irq2e bit is set to 0. example 2 C pu lsed interrupt once per minute (im = 1) interrupts at one minute intervals when the seconds register is at 30s. a. set alarm registers as follows: b. set the interrupt register as follows: once the registers are set, the following waveform will be seen at irq : note that the status re gister alm bit will be set each time the alarm is triggered, but does not need to be r ead or cleared. alarm register bit description 76543210hex sca 00000000 00hsec onds disabled mna 10110000 b0hminutes se t to 30, enabled hra 10010001 91hhours se t to 11, enabled dta 10000001 81hdate se t to 1, enabled moa 10000001 81hmonth se t to 1, enabled dwa 00000000 00hday of week disabled control register bit description 76543210hex int 01xx0000 x0he nable alarm note: x indicate ot her control bits alarm register bit description 76543210hex sca 10110000b0hsec onds set to 30, enabled mna 00000000 00hminutes disabled hra 00000000 00hhours disabled dta 00000000 00hdate disabled moa 00000000 00hmonth disabled dwa 00000000 00hday of week disabled control register bit description 76543210hex int 11xx0000 x0he nable alarm and int mode note: x indicate ot her control bits control register bit description 76543210hex 60s rtc and alarm regis ters are both 30s
isl12082 fn6731 rev 4.00 page 16 of 28 sep 25, 2015 timer control register (tmrc) [address 09h] timer clock frequency selection bits (tclk <1:0>) for detailed timer operation, please refer to timer counter operation on page 17. these bits select the timer/ watchdog clock frequency for the timer counter register (tcnt, address 13h) and the internal sub-timer counter register (tscnt). when the sub-timer initial register (tsdat, address 14h) is set to 0, the number of counts changes to the defaul t value. the maxi mum register value for the tsdat register is 127 which means the maximum limit for the internal sub-timer counter register is also 127. see table 10 for timer/watchdo g clock frequency selection and the default counts for the sub-timer counter register. the timer counter and sub-timer counter registers advance the counter value based on the frequency or time setting by the tclk<1:0> bits. the following are examples of timer clock frequency selection bits on timer counter and s ub-timer counter registers. example 1 - tclk1 is set to 1 , tclk0 is set to 0, and sub- timer initial register is set to 0. the internal sub-timer counter will increment every 1s . when the internal sub-timer counter reaches to 60, the default value, the timer counter will increment by one which me ans the timer counter will increment every one minute. example 2- tclk1 is set to 1 , tclk0 is set to 0, and sub- timer initial register is set to 10d. the internal sub-timer counter will increment every 1s . when the internal sub-timer counter reaches to 10, the tim er counter will increment by one which means the timer coun ter will increment every ten seconds. example 3- tclk1 is set to 0 , tclk0 is set to 1, and sub- timer initial register is set t o 0. the internal sub-timer counter will increment every 1m s (100hz). when the internal sub-timer counter reaches to 100, the default value2, the timer counter will increment by one which means the timer counter will increment every one second. timer function selecti on bits (t mod <1:0>) the timer interrupt has f our different functions: 1. count down timer 2. secondary alarm timer 3. watchdog timer 4. power fail count-up timer please see table 11 for timer counting functions selection. timer enable bit (tmre) this bit enables/disables the t imer function. when the tmre bit is set to 1, the timer is e nabled. to display timer inter rupt on the irq2 pin, the irq2e has to be set to 1. when the tmre bit is cleared to 0, the timer function is disabled. the tmre bit is set to 0 on power-up. timer pulse/event i nterrupt bit (tim) this bit enables/disables the i nterrupt mode of the timer function. when the tim bit is set to 1, the timer will operat e in the interrupt mode. an active low pulse width of 210ms will appear at the irq2 pin when the rtc is t riggered by the timer as defined by the tim er registers (12h to 15h). when the tim bit is cleared to 0 , the timer will oper ate in standard mode, where the irq2 pin will be held low un til tmr status bit is cleared to 0. the tim bit is set to 0 on power-up. table 9. timer control register (tmrc) addr 7 6 5 4 3 2 1 0 09h tim tmre tmod1 tmod0 0 0 tclk1 tclk0 default 0 0 0 0 0 0 0 0 table 10. timer clock frequency selection and default value for tsdat register tclk1 tclk0 function comment 0 0 100hz/4khz 100hz for tcnt, 4khz for tscnt default value for tsdat = 41 (41 tscnt counts = 1ms) (not available for watchdog timer) 0 1 1sec/100hz 1sec for tcnt, 100hz for tscnt default value for tsdat = 100 (100 tscnt counts = 1s) 1 0 1min/1sec 1min for tcnt, 1sec for tscnt default value for tsdat = 60 (60 tscnt counts = 1min) (rtc must be enabled) 1 1 1hr/1min 1hour for tcnt, 1min for tscnt default value for tsdat = 60 (60 tscnt counts = 1hr) (rtc must be enabled) table 11. timer counting function selection tmod1 tmod0 function comment 0 0 count down timer basic count down timer (tcnt register decrement) 0 1 secondary alarm timer basic count down timer activated by alarm irq (alm bit) (tcnt register decrement) 1 0 watchdog timer count up timer with periodic interrupt (tcnt register increment) 11power fail count-up timer count up after device entered into battery mode (tcnt register increment) tim bit timer pulse/event interrupt function 0 single time event set by timer 1 repetitive/recurring time event set by timer
isl12082 fn6731 rev 4.00 page 17 of 28 sep 25, 2015 timer registers addresses [12h to 15h] timer initial register (tdat) [address 12h] the timer initial register is located in the memory map at address 12h. this is a volatile register that stores the timer limit for the timer counter register. timer counter register (tcnt) [address 13h] the timer counter register is l ocated in the memory map at address 13h. this is a volatile register that ke eps the current timer counter value. this byte is read only. sub-timer initial regist er (tsdat) [address 14h] the sub-timer initial register i s located in the memory map at address 14h. this is a volatile register that stores the timer limit for the internal sub-timer counte r register. this byte is write only and only read back a 0 internal sub-timer coun ter register (tscnt) the internal sub-timer counter register is an internal volatile register that keeps th e current sub-timer counter value. this byte is not accessible. timer counter operation the isl12082 timer consists of a timer counter and a sub-timer counter. the timer counter c an be an incremental or a decremental counter which depends on the setting of the timer function selection bits (tmod[1 :0], address 09 h, bits 5 and 4). sub-timer counter works as an incremental counter. the timer counter is represented b y the timer counter register (tcnt, address 13h) and the sub-timer counter is represented by the internal sub-timer counte r register (tscnt) which is not accessible by the user. the t imer initial register (tdat, address 12h) and the sub-timer initial register (tsdat, address 14h) are used to set the limit for the tcnt register and internal tscnt register respectively. the tdat register must contain a minimum value o f 2 in order to operate the timer properly and the tsat r egister can be set to any value up to 127 decimal. if the tsdat register is set to 0, the tsdat will reset to the default value which depends on the tclk[1:0] bits setting which is shown in table 10. once the timer function is enabl ed by setting the tmre bit to 1, the tcnt register is set to the tdat value or one depending on the setting of the tmod[1:0] bits, and the internal tscnt register is set to one. then the internal tscnt will increment one bit at a time and at a frequ ency set by the timer clock frequency selection bits ( tclk[1:0], address 09h bits 1 and 0). the internal tscnt register will overflow when it counts up to the value in the tsdat register. if the tsdat register is set to 0, th e internal tscnt will count up to the default tsdat register val ue to overflow. if the interna l tscnt register overf lows, the tcnt regist er will increment or decrement by one depending on t he setting of t he tmod[1:0] bits and the internal tscnt r egister resets back to 1 and repeats the c ounting cycle. the timer expires when the tcnt register increments to the tda t register value or decrements to zero depending on the setting of the tmod[1: 0] bits. the tmr bit is set and the irq2 is held low to indicate the timer interrupt. the irq2 only activates for t he timer interrupt when the irq2e (address 8h, bit 3) sets to 1. table 12. timer initial register (tdat) addr76543210 12h tdat7 tdat6 tdat5 tdat4 tdat3 tdat2 tdat1 tdat0 default00000000 table 13. timer counter register (tcnt) addr76543210 13h tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 default00000000 table 14. sub-timer initial register (tsdat) addr76543210 14h tsdat7 tsdat6 tsdat5 tsdat4 tsdat3 tsdat2 tsdat1 tsdat0 default00000000
isl12082 fn6731 rev 4.00 page 18 of 28 sep 25, 2015 there are two ti mer operation mo des for the irq2 : single event and periodic interrupt mode: ? single event mode is enabled by setting the tmre bit to 1, the tim bit to 0, an d irq2e bit to 1. this mode permits a one-time timer counting cycle. once th e timer expires, the tmr status bit is set to 1 and the irq2 output will be held low until the tmr status bit is reset to 0. this can be done manually o r by using the auto-reset featur e. once the tmr status bit is reset, the timer will reset and restart the counting cycle. if the tmre bit is set to 0 before th e tmr status bit is reset, then counting is halted. the irq2 can be reset by setting th e tmre bit to 0 but the tmr status bit will remain at 1. the timer can be re-enabled with tmr status remaining at 1. ? periodic interrupt mode is enabled by setting the tmre bit to 1, the tim bit to 1, and irq2e bit to 1. the timer mus t be disabled prior to setting tim bit to 1 in order to enable the periodic interrupt mode. in the periodic interrupt mode, the irq2 output will be pulsed each time a timer expires. the low and the high pulse width of the irq2 can be calculated by the tclk[1:0] bit s, the tdat register and the tsdat register. after the interrupt, the internal tscnt register will keep counting until it overflows. when the internal tscnt register overflows, the irq2 pin is pulled high and the tscnt r egister is reset to the value in tdat register or 1 depended on the tmod[1:0] setting. then the new counting cycle begins. the tmr bit is still set each time when the timer expired. resetting the tmr stat us bit to 0 from 1 in the periodic interrupt mode will cause the tcnt register and the internal tscnt register to reset. de pending on when the tmr bit is being reset, the low pulse width or the high pulse width will be prolonged for the amount of time the counter has counted. the interrupt mode can be disabl ed by setting the tim bit to 0 when timer is e nabled. the interrupt mode can not be enabled after the timer is enabled. when the timer is disa bled by setting the tm re bit to 0, the register value for the timer co unter and the sub-timer are set back to the default value. th e default value for the timer counter register (tcnt, addres s 13h) is 0 and sub-timer counter register (tscnt, address 15h) is 1. following are the detailed descri ptions of the four different timer modes. count down timer the count down timer is a basic countdown timer. once the timer is enabled by setting tmre bit to 1, the tcnt register is set to the value in tdat register. the tdat register must have a value of two or greater in order for the timer to start. if the timer is enabled with tdat register less than two, then the timer is disabled and the tdat register has to be set to an appropriate value before the ti mer can be enabled again. the internal tscnt register in crements from one, and the incremental frequency is set by the tclk[1:0] bits. once the internal tscnt register ove rflows, the tcnt register will decrement by one and the intern al tscnt register will reset back to one and start counting a gain until the tcnt register reaches zero. once the tcnt reg ister reaches zero, the timer will issue an interrupt that wil l set the tmr status bit to 1 and set the irq2 pin to low (if irq2e bit is set to 1). when the tim = 0 (single event mode), the timer stops after the timer expires. the timer will restart and the irq2 pin will be high when the tmr bit is clear ed to 0. the tim er can also be restarted by resetting the tmre bit to 1 after setting it to 0. this method is not recommended since the tmr status will not clear by this method and may ca use confusion in the system. in single event mode, t he time interval for the timer expiratio n is calculated by using equation 3. where, tdat is the value in the tdat register. tsdat is the value in the tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits . for 4khz setting, please use 244s for the period. for 100hz s etting please use 10ms for the period. when the tim = 1 (periodic interrupt mode), the timer repeats the countdown functi on automatically after the timer expires. the periodic interrupt function ca n only be monitored on the irq2 pin; therefore, the irq2e bit must be set to 1 to show timer interrupt on the irq2 pin. the irq2 pin is pulsed each time the timer expires. once the timer expires, the tmr status bit set to 1 and the irq2 pin goes low. the internal tscnt register will reset and contin ue counting. once the internal tscnt overflows after t he timer expires, the irq2 pin will pull back to high but the tmr status bit will remain at 1 until th e user clears it. the tcnt register will reset back to the value in the tdat register to start the new count cycle. t he timer will continue counting until the tmre = 0 to disable the timer. in periodic interrupt m ode, the time inter val for the timer expiration is calculated differen tly for the first timer expira tion and for the next and succeeding ti mer expiration. for the first timer expiration, t he time interval is calculated by using equation 3. for the next and su cceeding timer expiration, the time interval can be treated as the high pulse width of irq2 pin (t high_cdt ), and it is calculated by using equation 4. the low interrupt pulse width of irq2 pin (t low_cdt ) is calculated by using equation 5. sin ce the tmr status bit is not reset automatically by the device at th e new count cycle , if the user resets it, the timer will rese t and the next co unt cycle will b e seen as the first coun t cycle by the device. where, tdat is the value in the tdat register. tsdat is the value in the tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits . for 4khz setting, please use timer interval = tdat*tsdat*tclk (eq. 3) t high_cdt = (tdat-1)*tsdat*tclk (eq. 4)
isl12082 fn6731 rev 4.00 page 19 of 28 sep 25, 2015 244s for the period. f or 100hz setting pl ease use 10ms for the period. where, tsdat is the value in t he tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits. for 4khz setting, please use 244s for the period. for 100hz setting please use 10ms for the period. since the pulse width of the irq2 pin is adjustable with setting in the tdat register, the tsda t register and the tclk[1:0] bits, the irq2 pin can be use as a variable frequency/pulse width generator. secondary alarm timer the secondary alarm timer fu nction has the exact same function as the count down time r function except the timer activates when the device has an alarm interrupt (alm set to 1) with tmre set to 1 to enable the timer. once the timer i s activated by the alarm inte rrupt, the timer will work independently. another alarm inte rrupt will not reset the timer function while the ti mer is counting. when the timer is stopped by the timer interrupt or disabl ed by the tmre bit, the timer has to wait for the new alarm inte rrupt to activate it. please refer to the count down time r on page 18 for the detailed timer function. watchdog timer the watchdog timer is used as an i 2 c bus activity monitor. if the i 2 c bus does not have an activity for a period of time which is longer than its normal condition, then the watchdog timer wi ll issue an interrupt to set the tmr status bit to 1 and pulse t he irq2 pin low for 210ms if irq2e bi t is set to 1 for timer interrupt. it is recommended to set the irq2e to 1 for irq2 pin to show the timer interrupt because the i 2 c may be in a fault condition where monitori ng the tmr status bit will be impossible. the watchdog timer is reset and will start a new count cycle by an i 2 c start cond ition on the i 2 c bus. the watchdog timer onl y works with the tclk [1:0] setting of 01, 10 and 11. the timer is disabled with the tclk[1:0] setting of 00. once the timer is enabled by s etting tmre=1, the tcnt register is set to 1 and counts up to the tdat register value . the tdat register must has a val ue of one or greater in order for the timer to start. if the timer is enabled with tdat regis ter less than one, then the timer is disabled and the tdat register has to be set to an appropriate value before t he timer can be enabled again. the internal tscnt register increments from one, and the incremental frequen cy is set by the tclk[1:0] bits. once the internal tscnt r egister overflows, the tcnt register will increment by one an d the internal tscnt register will reset back to one and start counting again until the tcnt register reaches the tdat regi ster value. once the tcnt register reaches the tdat regist er value, the timer will issue an interrupt that will set the tm r status bit to 1. the irq2 pin will pulse low for 210ms if the i rq2e bit is set to 1 for tim er interrupt and tsdat register is set to 0 for default count value (refer to table 10 for the default count values). the tim er will reset and start a new coun t cycle after the interrupt; therefore, the watchdog timer is in periodic interrupt mode onl y with tim bit set to 0 or 1. the time interval fo r the watchdog inte rrupt is calculated differently for the first watc hdog interrupt and for the next a nd succeeding watchdog interrupt. for the first watchdog interrupt (t wd_1st ), the time interval is calcu lated by using equation 6. for the next and succeeding watchdog interrupt (t wd_2nd ), the time interval is calculated by using equation 7. the low interrupt pulse width of irq2 pin (t wd_irq ) is calculated by using equation 8. the interrupt pulse width has a maximum pulse width of 210ms. if the in terrupt is less than 210ms, then the remaining time (210ms-act ual interrupt pulse) from the interrupt pulse width will be add ed to the time interval of the next count cycle. where, tdat is the value in the tdat register. tsdat is the value in the tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits. for 100hz setting, please use 10ms for the period. where, tdat is the value in the tdat register. tsdat is the value in the tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits. for 100hz setting, please use 10ms for the period. note: apply equati on 7 only when t wd_irq is greater than 210ms. t low_cdt = tsdat*tclk (eq. 5) t wd_1st = tdat*tsdat*tclk (eq. 6) t wd_2nd = (tdat-1)*tsdat*tclk+[(t wd_irq )-210ms] (eq. 7) t wd_irq (maximum 210ms) = tsdat*tclk (eq. 8)
isl12082 fn6731 rev 4.00 page 20 of 28 sep 25, 2015 where, tsdat is the value in t he tsdat register (use default if 0). tclk is the period set by the tclk[1:0] bits. for 100hz setting, please use 10ms for the period. power fail timer in power fail timer function, the timer will start counting whe n the device is switc hed from normal mode to battery mode. the power fail timer only works with the tclk[1:0] setting of 01, 10 and 11. the timer is disabled with the tclk[1:0] setting of 00. once the timer is enabled by se tting tmre bit to 1 and the device switches from normal mode to battery mode, the tcnt register is set to 1. the time r expires when tcnt counts to ffh (255d) and the value in the tdat register is ignored. the internal tscnt register increments from one, and the incremental frequency is set by the tclk[1:0] bits. once the internal tscnt register ov erflows, the tcnt register increments by one and the internal tscnt register resets back to one and starts counting agai n until the tcnt register reaches ffh (255d). once the tcnt register reaches ffh (255d), the timer issues an interrupt to set the tmr status bit to 1 and pull irq2 pin low if irq2e = 1 (timer interrupt). the timer stops after the time exp ires, and the power fail timer is in single event mode only regarding the status of tim bit. the timer restarts and the irq2 pin pulls high when the tmr bit is cleared by the user. the timer c an also restart by resetting th e tmre bit to 1 after setting it t o 0 but this m ethod is not recommended since the tmr stat us will not clear by this method and may cause confusio n in the system. in single event mode, the time interval for the timer expiration is calculated by using equation 3. the power fail timer will store the timer value in the tcnt register after the device switc hes back to normal mode from battery mode. the next time th e device enters battery mode from normal mode, the t imer will start its count from the value stored in the tcnt register. the stored value in tcnt register is only clear when the timer is disabled by setting the tmre bi t to 0. i 2 c serial interface the isl12082 supports a bi-dire ctional bus oriented protocol. the protocol defines any device that send s data onto the bus as a transmitter and the receivi ng device as the receiver. the device controlling the transfer i s the master and the device being controlled is the slave. th e master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl12082 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 12). on power-up of the isl12082, the sd a pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to low transition of sda while scl is high. the isl12082 continuou sly monitors the sda and scl lines for the start condit ion and does not respond to any command until this condition is met (see figure 12). a start condi tion is ignored during the power-up sequence.
isl12082 fn6731 rev 4.00 page 21 of 28 sep 25, 2015 all i 2 c interface operations mus t be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 13). a stop condition at the end of a read operation or at the end of a wri te operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a succe ssful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during t he ninth clock cycle, t he receiver pulls th e sda line low to acknowledge the reception of the eight bits of data (see figure 14). the isl12082 responds with an ack after recognition of a start condition followed by a v alid identificat ion byte, and once again after succe ssful receipt of an address byte. the isl12082 also responds with an ack after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation. device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifier. these bits are 1101111. slave bits 1101 access the register. slave bit s 111 specify the device select bits. the last bit of the slave addre ss byte defines a read or write operation to be performed. when this r/w bit is a 1, then a read operation is selected. a 0 selects a write operation (se e figure 15). after loading the entire slave address byte from the sda bus, the isl12082 compares the device identifier and device select bits with 1101111 . upon a correct compare, the device outputs an acknowled ge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained sda scl start data data stop stable change data stable figure 12. valid data changes, start, and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 13. acknowledge response from receiver s t a r t s t o p identification byte first data byte a c k signals from the master signals from the isl12082 a c k 10 0 11 a c k write signal at sda 0000 111 address byte a c k last data byte a c k figure 14. sequential byte write sequence
isl12082 fn6731 rev 4.00 page 22 of 28 sep 25, 2015 from an internal counter. on power-up the internal address counter is set to address 0h, so a current address read of the ccr array starts at address 0h. when required, as part of a random read, the ma ster must supply t he 1 word address bytes as shown in figure 16. in a random read oper ation, the slave byte in the dummy write portion must m atch the slave byte i n the read section. for a random read of the clock/control re gisters, the slave byte must be 1101111x in both places. write operation a write operation requires a sta rt condition, followed by a valid identification byte, a valid address byte, a data byte, a nd a stop condition. after each o f the three bytes, the isl12082 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a t hree byte instru ction followed by one or more data bytes (s ee figure 16). the master initiates the operation issuing the following sequence: a start, the identificatio n byte with the r/w bit set to 0, an address byte, a second start , and a second i dentification byte with the r/w bit set to 1. after each of the three bytes, the isl12082 respon ds with an ack. then the isl12082 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see fi gure 16). the data bytes are from the memo ry location indicated by an internal pointer. this pointer in itial value is determined by t he address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory locatio n 13h the pointer rolls over to 00h, and the device continue s to output data for each ack received. figure 15. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address figure 16. sequential byte read sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11
isl12082 fn6731 rev 4.00 page 23 of 28 sep 25, 2015 application section oscillator crys tal requirements the isl12082 uses a standard 32.768khz crystal. either through hole or surface mount cr ystals can be used. table 15 lists some recommended surface mount crystals and the parameters of each. this lis t is not exhaustive and other surface mount devices can be u sed with the is l12082 if their specifications are very simila r to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent series resistance of <50k. the crystals temperatur e range specification should match the application. many crystals are rated for -10c to +60c (especially through-hole and t uning fork types), so an appropriate crystal should be selected if extended temperature range is required. crystal oscillator frequency adjustment the isl12082 device contains c ircuitry for adjusting the frequency of the crystal oscillat or. this circuitry can be used to trim oscillator initial accuracy as well as adjust the frequenc y to compensate for tem perature changes. the analog trimming register (atr) is used to adjust the load capacitance seen by the cryst al. there are 6 bits of atr control, with linear capacitance increments available for adjustment. since the atr adjust ment is essentially pulling the frequency of the oscillator, the resulting frequency change s will not be linear with incremental capacitance changes. the equations which govern pulling show that lower capacitor values of atr adjustm ent will provide larger increments. also, the higher values of atr adj ustment will produce smaller incremental frequency changes. these values typically vary from 6ppm to 10ppm/bit at th e low end to <1ppm/bit at the highest capacitance settings. the range afforded by the atr adjustment with a typical surfac e mount crystal is typically - 34ppm to +80ppm around the atr = 0 default setting because of this property. the user should note this when using the atr for calibration. the temperature drift of the capacitance used in the atr control is ext remely low, so this feature c an be used for temperature compens ation with good accuracy. in addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the isl12082. there are 6 bits known as the digit al trimming register (dtr). the range provided is 63.0696ppm to +126.139ppm. dtr operates by adding or skipping pulses in the clock counter. it is very useful for coarse adjustments of frequency drift over-temperature or extending t he adjustment range available with the atr register. initial accuracy is best adjusted by enabling the frequency output (using the int register , address 08h), and monitoring the ~irq/f out pin with a calibrated frequency counter. the frequency used is unimportant, a lthough 1hz is the easiest to monitor. the gating time shoul d be set long enough to ensure accuracy to at least 1ppm. the atr should be set to the center position, or 100000b h, to begin with. o nce the initial measurement is made, then the atr register can be changed to adjust the frequency . note that increasing the atr register for increased capacitance will lower the frequency, and vice- versa. if the initial measuremen t shows the frequency is far of f, it will be necessary to use the dtr register to do a coarse adjustment. also, not e that most all crys tals will have tight enough initial accuracy at room temperature so that a small atr register adjustment should be all that is needed. temperature compensation the atr and dtr controls can be combined to provide crystal drift temperature compensation. the typical 32.768khz crystal has a drift characteristic that i s similar to that shown in fig ure 17. there is a turnover-temperature (t 0 ) where the drift is very near zero. the shape is parabolic as it varies with the square of the difference between t he actual temperature and the turnover-temperature. if full industrial temperature co mpensation is desired in an isl12082 circuit, then both th e dtr and atr registers will need to be utilized (total co rrection range = -97ppm to +206ppm). a system to implement tempe rature compensation would consist of the isl12082, a tempe rature sensor, and a micro controller. these devices may a lready be in the system so the function will just b e a matter of implementing software and performing some calculations. fairly accurate temperature compensation can be implemented just by using the crystal table 15. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 temperature (c) -160 -140 -120 -100 -80 -60 -40 -20 0 -40-30-20-100 1020304050607080 ppm figure 17. rtc crystal temperature drift
isl12082 fn6731 rev 4.00 page 24 of 28 sep 25, 2015 manufacturers specifications f or the turnover-temperature t 0 and the drift coefficient ( ? ). the formula for calculating the oscillator adjustment necessa ry is shown in equation 9: once the temperature curve for a crystal is established, then the designer should dec ide at what discrete temperatures the compensation will change. since drift is higher at extreme temperatures, the compensatio n may not be n eeded until the temperature is great er than +20c from t 0 . a sample curve of the atr se tting vs frequency adjustment for the isl12082 and a typica l rtc crystal is given in figure 18. this curve ma y vary with differen t crystals, so it is good practice to evaluate a given crystal in an isl12082 circui t before establishing the adjustment values. this curve is then used to fig ure what atr and dtr settings are used for compensation. the r esults would be placed in a lookup table for the mi crocontroller to access. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operati ng at low frequencies such as 32.768khz are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clockin g or large accuracy errors can be t raced to the susceptibility of the oscillator circuit to interfe rence from adjacent high speed clock or data lines. careful la yout of the rtc circuit will avo id noise pickup and insure accurate clocking. figure 19 shows a s uggested layout for the isl12082 device using a surface mount crystal. two main precautions should be followed: 1. do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the oscillator circuit to cause misclocking. 2. add a ground trace aroun d the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vi cinity of the rtc device. in addition, it is a good idea t o avoid a ground plane under th e x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circui t. if the irq1 /f out pin is used as a clock, it should be routed away from the rtc device as well. the trace s for the v bat and v cc pins can be treated as a ground, and should be routed around the crystal. supercapacitor backup the isl12082 device provides a v bat pin which is used for a battery backup input. a superc apacitor can be used as an alternative to a battery in ca ses where shorte r backup times are required. since the battery b ackup supply current required by the isl12082 is extremely low , it is possible to get months of backup operation us ing a supercapacitor. typical capacitor values are a few f to 1f or more depending on the application. if backup is only needed for a few minutes, then a small inexpensive electrolytic capaci tor can be used. for extended periods, a low leakage, high capacity supercapacitor is the best choice. these devices are available from such vendors as panasonic and murata. the main specifications include working voltage and leakage curr ent. if the application is for charging the capacitor from a +5v 5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5v to slightly over 5.0v. a capacito r with a rated wv of 5.0v may have a reduced lifetime if the supply voltage is slightly high. the leakage current should be as small as possible. for example, a supercapacitor should be specified with leakage of well below 1a. a standard el ectrolytic cap acitor with dc leakage current in the micr oamps will have a severely shortened backup time. following are some examples with equations to assist with calculating backup times and required capacitance for the isl12082 device. the backup suppl y current plays a major part in these equations, and a ty pical value was chosen for example purposes. for a robus t design, a margin of 30% should be included to cover s upply current and capacitance tolerances over the results o f the calculations. even more margin should be included if periods of very warm temperature operation are expected. adjustment(ppm) t t 0 C ?? 2 = ? ? (eq. 9) -400 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 50 55 60 atr setting ppm adjustment figure 18. atr setting vs oscillator frequency adjustment figure 19. suggested layout for isl12082 and crystal u1 1 y1
isl12082 fn6731 rev 4.00 page 25 of 28 sep 25, 2015 example 1. calculating backup time given voltages and capacitor value in figure 20, use c bat = 0.47f and v cc = 5.0v. with v cc = 5.0v, the voltage at v bat will approach 4.7v as the diode turns off completely. the isl12082 is specified to operate down to v bat = 1.8v. the capacitance charge/discharge equation is us ed to estimate the total backup time as shown in equation 10: rearranging gives equation 11. c bat is the backup capacitanc e and dv is t he change in voltage from fully charged to loss of operation. note that i tot is the total of the supply current of the isl12082 (i bat ) plus the leakage current of the ca pacitor and the diode, i lkg . in these calculations, i lkg is assumed to be extremely small and will be ignored. if an application requi res extended operation at temperatures over +5 0c, these leakages will increase and hence reduce backup time. note that i bat changes with v bat almost linearly (see typical performance curves on page 7) . this allows us to make an approximation of i bat , using a value midway between the two endpoints. the typical linear equation for i bat vs v bat is shown in equation 12: using this equation to solve for the average current given 2 voltage points gives equation 13: combining with equation 11 gives the equation for backup time in equation 14: where: c bat = 0.47f v bat2 = 4.7v v bat1 = 1.8v i lkg = 0 (assumed minimal) solving equation 13 for this example, i batavg = 4.387e-7 a t backup = 0.47 * (2.9) / 4. 38e-7 = 3.107e6 sec since there are 86,400 seconds in a day, this corresponds to 35.96 days. if the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be: example 2. calculating a ca pacitor value for a given backup time referring to figure 20 again, the capacitor value needs to be calculated to give 2 months ( 60 days) of backup time, given v cc = 5.0v. as in example 1, the v bat voltage will vary from 4.7v down to 1.8v. we will need to rearrange equation 11 to solve for capacitance in equation 16: using the terms previously, this equation 16 becomes equation 17: where: t backup = 60 days*86,400 sec/ day = 5.18 e6 seconds i batavg = 4.387 e-7 a (sam e as example 1) i lkg = 0 (assumed) v bat2 = 4.7v v bat1 = 1.8vsolving gives c bat = 5.18 e6*(4.387 e-7)/(2.9) = 0.784f if the 30% tolerance is included for tolerances, then worst case capacitor value woul d be as shown in equation 18. figure 20. supercapacitor charging circuit 2.7v to 5.5v v cc v bat gnd 1n4148 c bat i = c bat dv/dt (eq. 10) dt = c bat dv/i tot to solve for backup time. (eq. 11) i bat = 1.031e-7(v bat ) + 1.036e-7a (eq. 12) i batavg = 5.155e-8(v bat2 + v bat1 ) + 1.036e-7a (eq. 13) t backup = c bat (v bat2 - v bat1 )/(i batavg + i lkg ) (eq. 14) seconds (eq. 15) c bat 0.70 35.96 25.2 = ? days = = = + - ==
fn6731 rev 4.00 page 26 of 28 sep 25, 2015 isl12082 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change september 25, 2015 fn6731.4 updated the ordering information tabl e on page 2. added revision history and about intersil sections. updated package outline drawing m8.15 to the latest revision. c hanges are as follows: -updated to new pod format by rem oving table and moving dimensi ons onto drawing and adding land pattern. -3/4/11 rev3 - changed in typical recommended land pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -changed note 1 "1982" to "1994"
isl12082 fn6731 rev 4.00 page 27 of 28 sep 25, 2015 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or ga te burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. package width does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are s hown for reference only. 6. the lead width as measured 0.36m m (0.014 inch) or greater abo ve the seating plane, shall not exceed a maximum value of 0.61mm (0.02 4 inch). 7. controlling dimension: millimete r. converted inch dimensions a re not necessarily exact. 8. this outline conforms to je dec publication ms-012-aa issue c . side view a side view b 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)
isl12082 fn6731 rev 4.00 page 28 of 28 sep 25, 2015 mini small outline pl astic packages (msop) notes: 1. these package dimensions are w ithin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gat e burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e1 does not include interlead flash or protrusion s and are measured at datum plane. interlead flash and protrusions shall not exceed 0. 15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another with in 0.10mm (.004) at seating plane. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of b dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x ? 4x ? gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - ? 0 o 6 o 0 o 6 o - rev. 0 12/02 ?

▲Up To Search▲

Price & Availability of ISL12082IB8Z-T

	To Download ISL12082IB8Z-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .